宋海浩, 延波, 倪小兵, 智强, 李梦依, 刘佳音, 任莹楠, 司可, 张琳琳. 一种像增强器阴极高重频选通电路的设计[J]. 应用光学, 2022, 43(6): 1187-1195. DOI: 10.5768/JAO202243.0604020
引用本文: 宋海浩, 延波, 倪小兵, 智强, 李梦依, 刘佳音, 任莹楠, 司可, 张琳琳. 一种像增强器阴极高重频选通电路的设计[J]. 应用光学, 2022, 43(6): 1187-1195. DOI: 10.5768/JAO202243.0604020
SONG Haihao, YAN Bo, NI Xiaobing, ZHI Qiang, LI Mengyi, LIU Jiayin, REN Yingnan, SI Ke, ZHANG Linlin. Design of high-repetition frequency gating circuit for cathode of image intensifier[J]. Journal of Applied Optics, 2022, 43(6): 1187-1195. DOI: 10.5768/JAO202243.0604020
Citation: SONG Haihao, YAN Bo, NI Xiaobing, ZHI Qiang, LI Mengyi, LIU Jiayin, REN Yingnan, SI Ke, ZHANG Linlin. Design of high-repetition frequency gating circuit for cathode of image intensifier[J]. Journal of Applied Optics, 2022, 43(6): 1187-1195. DOI: 10.5768/JAO202243.0604020

一种像增强器阴极高重频选通电路的设计

Design of high-repetition frequency gating circuit for cathode of image intensifier

  • 摘要: 就距离选通技术对阴极选通信号要求重复频率高、边沿速度快、脉冲宽度小,提出了一种利用分阶段、多级加速工作的阴极高重频选通电路。通过将RC电路与高速门电路组合构成的时间偏置电路单元相互级联产生不同时序的逻辑脉冲,分别控制中间级驱动金属氧化物半导体场效应晶体管(MOSFET)产生3个阶段性的驱动信号,中间级驱动的输出作为输出级MOSFET的栅极输入,控制其通断过程的加速与保持。利用软件仿真以及板级测试的方式进行了验证,试验结果表明,提出的选通电路可将输出脉冲的边沿时间由μs级提升至2 ns,可提供+50 V/−200 V的阴极关闭/开启电压,实现0~350 kHz的重复频率,0~100%的占空比,3.7 ns的最小脉冲宽度,脉冲输出延时时间抖动在0.1 ns左右。对于提升高速高压选通电源的最小脉冲宽度性能、最高工作重复频率以及降低器件功率损耗具有重要的指导意义。

     

    Abstract: According to the requirements of high repetition frequency, fast edge speed and small pulse width for cathode gating signal by range-gated technology, a cathode high repetition frequency gating circuit using period and multi-stage acceleration was proposed. By combining the RC circuit and the high-speed gate circuit, the time bias circuit unit was cascaded to generate logic pulses with different time sequences, which could respectively control the intermediate stage drive MOSFET to generate three phased drive signals, and the output of the intermediate stage drive was used as input of the output-stage MOSFET to control the acceleration and retention of its on-off process. It was verified by software simulation and board-level test. The test results show that the proposed gating circuit can increase the edge time of output pulse from μs level to 2 ns, and can provide +50 V/−200 V cathode off/on voltage, so as to achieve a repetition frequency ranging from 0~350 kHZ, a duty ratio of 0~100%, a minimum pulse width of 3.7 ns, and a pulse output delay time jitter of about 0.1 ns. It has important guiding significance for improving the minimum pulse width performance of high-speed and high-voltage gating power, the highest working repetition frequency and reducing the power loss of the device.

     

/

返回文章
返回