一种像增强器阴极高重频选通电路的设计

宋海浩; 延波; 倪小兵; 智强; 李梦依; 刘佳音; 任莹楠; 司可; 张琳琳

doi:10.5768/JAO202243.0604020

一种像增强器阴极高重频选通电路的设计

doi: 10.5768/JAO202243.0604020

宋海浩^{1, 2,},
延波^{1, 2},
倪小兵^{1, 2},
智强^{1, 2},
李梦依^{1, 2},
刘佳音^{1, 2},
任莹楠^{1, 2},
司可^{1, 2},
张琳琳^{1, 2}

1.
微光夜视技术重点实验室，陕西西安 710065
2.
昆明物理研究所，云南昆明 650223

基金项目: 国防基础科研项目（JCKY2018208B016）

详细信息

作者简介:
宋海浩（1995—），男，硕士，助理工程师，主要从事电子学在微光夜视技术中的应用。E-mail：songhaihao95@163.com

中图分类号: TN710
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- 文章访问数: 99
- HTML全文浏览量: 44
- PDF下载量: 14
- 被引次数: 0
出版历程
- 收稿日期: 2022-08-12
- 修回日期: 2022-09-25
- 网络出版日期: 2022-09-28
- 刊出日期: 2022-11-14

Design of high-repetition frequency gating circuit for cathode of image intensifier

SONG Haihao^{1, 2
,},
YAN Bo^{1, 2},
NI Xiaobing^{1, 2},
ZHI Qiang^{1, 2},
LI Mengyi^{1, 2},
LIU Jiayin^{1, 2},
REN Yingnan^{1, 2},
SI Ke^{1, 2},
ZHANG Linlin^{1, 2}

1.
Science and Technology on Low-Light-Level Night Vision Laboratory, Xi'an 710065, China
2.
Kunming Institute of Physics, Kunming 650223, China

摘要

摘要: 就距离选通技术对阴极选通信号要求重复频率高、边沿速度快、脉冲宽度小，提出了一种利用分阶段、多级加速工作的阴极高重频选通电路。通过将RC电路与高速门电路组合构成的时间偏置电路单元相互级联产生不同时序的逻辑脉冲，分别控制中间级驱动金属氧化物半导体场效应晶体管(MOSFET)产生3个阶段性的驱动信号，中间级驱动的输出作为输出级MOSFET的栅极输入，控制其通断过程的加速与保持。利用软件仿真以及板级测试的方式进行了验证，试验结果表明，提出的选通电路可将输出脉冲的边沿时间由μs级提升至2 ns，可提供+50 V/−200 V的阴极关闭/开启电压，实现0～350 kHz的重复频率，0～100%的占空比，3.7 ns的最小脉冲宽度，脉冲输出延时时间抖动在0.1 ns左右。对于提升高速高压选通电源的最小脉冲宽度性能、最高工作重复频率以及降低器件功率损耗具有重要的指导意义。
- 像增强器 /
- 选通电路 /
- MOSFET /
- 高重频
Abstract: According to the requirements of high repetition frequency, fast edge speed and small pulse width for cathode gating signal by range-gated technology, a cathode high repetition frequency gating circuit using period and multi-stage acceleration was proposed. By combining the RC circuit and the high-speed gate circuit, the time bias circuit unit was cascaded to generate logic pulses with different time sequences, which could respectively control the intermediate stage drive MOSFET to generate three phased drive signals, and the output of the intermediate stage drive was used as input of the output-stage MOSFET to control the acceleration and retention of its on-off process. It was verified by software simulation and board-level test. The test results show that the proposed gating circuit can increase the edge time of output pulse from μs level to 2 ns, and can provide +50 V/−200 V cathode off/on voltage, so as to achieve a repetition frequency ranging from 0~350 kHZ, a duty ratio of 0~100%, a minimum pulse width of 3.7 ns, and a pulse output delay time jitter of about 0.1 ns. It has important guiding significance for improving the minimum pulse width performance of high-speed and high-voltage gating power, the highest working repetition frequency and reducing the power loss of the device.
- image intensifier /
- gating circuit /
- MOSFET /
- high repetition frequency

HTML全文

图 1 像增强器结构

Fig. 1 Structure diagram of image intensifier

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图 2 阴极选通信号需求

Fig. 2 Demand diagram for cathode gating signal

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图 3 MOSFET等效电路

Fig. 3 Equivalent circuit diagram of MOSFET

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图 4 输出级驱动电路

Fig. 4 Diagram of output-stage drive circuit

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图 5 D触发器时间偏置电路单元原理图

Fig. 5 Schematic diagram of time bias circuit unit of D flip-flop

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图 6 D触发器时间偏置电路单元仿真

Fig. 6 Simulation of time bias circuit unit of D flip-flop

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图 7 D触发器时间偏置电路2级级联偏置仿真

Fig. 7 Simulation diagram of two-stage cascaded bias of D flip-flop time bias circuit

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图 8 死区时间控制单元电路

Fig. 8 Circuit diagram of dead time control unit

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图 9 死区时间时序逻辑

Fig. 9 Diagram of dead time sequential logic

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图 10 最小脉宽微调电路

Fig. 10 Diagram of minimum pulse width trimming circuit

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图 11 最小脉宽微调的时序逻辑

Fig. 11 Diagram of sequential logic of minimum pulse width trimming

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图 12 驱动逻辑框图

Fig. 12 Block diagram of drive logic

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图 13 部分驱动逻辑

Fig. 13 Diagram of partial drive logic

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图 14 加速导通(一级驱动)电路

Fig. 14 Accelerated conduction (primary drive) circuit

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图 15 加速导通驱动信号

Fig. 15 Accelerated conduction drive signal

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图 16 信号保持(一级驱动)电路

Fig. 16 Signal holding (primary drive) circuit

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图 17 加速关断(一级驱动)电路

Fig. 17 Accelerated shutdown (primary drive) circuit

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图 18 硬件设计

Fig. 18 Hardware design

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图 19 测试平台

Fig. 19 Test platform

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图 20 加速前的上升边沿

Fig. 20 Diagram of rising edge before acceleration

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图 21 加速后的上升边沿

Fig. 21 Diagram of rising edge after acceleration

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图 22 最小脉冲宽度输出

Fig. 22 Diagram of minimum pulse width output

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图 23 选通电路高重频测试

Fig. 23 Diagram of high repetition frequency test for gating circuit

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图 24 波形抖动测试

Fig. 24 Diagram of waveform jitter test

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